With the advancement in semi-conductor fabricating technology and the push for upgrade in semiconductor chip circuitry capability, the trend of semiconductor packaging moves towards high integration. The Ball Grid Array (BGA) packaging method and the FCBGA packaging method are currently replacing the traditional semiconductor package with a lead frame. BGA packaging method allows for more I/O connections per unit surface thus allowing more circuitry and semiconductor chips to be accommodated therein.
However as the semiconductor packaging becomes highly integrated, the number of connection leads also increases. This along with the increased number of semiconductor circuitry results in a corresponding increase in noises. Typically to eliminate these noises or to achieve electrical performance compensation, a way is to embed passive components, such as capacitor components, into the semiconductor package so as to stabilize the circuitry and allow the semiconductor package to meet the requirement of satisfactory electrical performance.
Conventionally, this is achieved by mounting capacitor components on the surface of a substrate. However the substrate structure when subjected to external environmental factor such as external vibration, the capacitor component may become dislodged due to weak bonding strength. Furthermore, typically in order to avoid capacitor component from obstructing the electrical connection between the semiconductor component and solder pad, the capacitor components are placed on surface areas of the substrate structure which are not occupied by the circuitry. This method requires larger substrate surface area resulting in an increase in the package size. Furthermore as capacitor components have to be separately mounted onto the substrate structure, this method also increases the complexity of the chip circuitry and the fabricating process.
Referring to FIG. 1, a plurality of capacitor components 12 are disposed on the surface of a substrate 1. The substrate 1 can be a typical printed circuit board or semiconductor substrate, however in order to avoid the capacitor components 12 from obstructing the electrical connections between the semiconductor chip 11 and a plurality of solder pads, the conventional way is to dispose the capacitor components 12 on the edge of the substrate surface or on the substrate surface outside the semiconductor chip mounting region whereon the semiconductor chip is to be mounted. However, as the positions of the solder pads must be considered, the disposition positions and numbers of the capacitor components 12 are limited. As the requirement for high electrical performance increases, the number of capacitor components required also increases. It is therefore unavoidable to increase the size of the package using the conventional method to dispose semiconductor chips 11 and a large number of capacitor components 12 on the substrate surface, thereby contradicting the trend towards miniaturization. In addition, this type of substrate structure is designed for a single electrical function, and is not flexibly modified to adapt and incorporate other electrical components or semiconductor component, as such when there is a need for a different capacitor component with different capacitance values, a new substrate structure 1 has to be designed. This results in an increase in complexity of the fabricating process of semiconductor.
As such, considering the trend of electronic product towards miniaturization, multiple functionalities and high electrical performance, the ability to embed sufficient numbers of capacitor components on a substrate structure, and increase the capacitor components and the substrate structure bonding strength, the ability to improve the capacitor components flexibility for change and also the flexibility for modification to the substrate structure circuitry design is therefore a topic needing urgent resolution.